Technical Skills
Verification
UVM
SystemVerilog
Formal Verification
Functional Coverage
Assertion Based Verification
Debugging
Hardware Design
Verilog
VHDL
FPGA
ASIC
RTL Design
Computer Architecture
Programming
C/C++
Python
Assembly
Bash/CSH
Perl
JavaScript
Tools & Frameworks
Vivado
Questasim
Git
Linux/UNIX
React
Tailwind CSS
Get In Touch
I'm currently looking for new opportunities in Design Verification and Hardware Engineering. Whether you have a question or just want to say hi, feel free to reach out!